A number of non-volatile memory (NVM) technologies, are co-existing in the unlimitedly repeat P/E market today. These NVMs include flash, battery-backed SRAM (BBSRAM), electrically erased programmable read-only memory (EEPROM) and NVSRAM, which integrates both NVM and SRAM in cell level within one monolithic chip.
Table 1 below provides a summary of the key features of these memory types.
ParametersNAND flashEEPROMBBSRAMNVSRAMNonvolatileYesYesYesYesUnlimitedNoNoYesYesenduranceRandom accessNoNoYesYesBattery needed?NoNoYesNoVCCcap needed?NoNoNoYesFast Read & WriteNoNoNoYes25-45nsByte-programmableNoYesYesYesFN-channel P/E?YesYesNoYesSBPI*YesNoNoYes*SBPI: Self-Boost-Program-Inhibit Scheme
The NAND flash memory is frequently used to store a huge Gb code and data in unit of a block size, ranging from 512 Kb to 2 Mb, for audio and video applications. Typically, the NAND flash read speed is 20 μs in a page is a NVM memory.
In contrast, the EEPROM memory is frequently utilized to store small amount of non-volatile configuration bits or data. However, compared with other non-volatile technologies, EEPROM density is lower with a slower Read speed of 100 ns and Write speed of 2 ms, making it unacceptable as a single memory technology for many medical applications.
The NAND flash is much cheaper than EEPROM in terms of bit price. But EEPROM has a superior 1M P/E endurance performance in unit of Byte over NAND's 100K in unit of Block. As a result, both NAND and EEPROM result in limited read/write cycles that can wear out the memory devices in repetitive applications, ultimately causing loss of data.
FIG. 1 shows two conventional 8-pin packages for an I2C Serial EEPROM product. The names of 8 pins are defined in order from pin1 to pin8 of A0, A1, A2, VSS, SDA, SCL, WP and VCC. There are no extra pins for connecting Vbat (battery) and Vcap (VCC capacitor) in addition to the regular VCC in pin1 of PDIP/SOIC/TSSOP/MSOP 8-pin package or VCC in pin2 of TSSOP 8-pin package.
In this conventional 8-pin I2C EEPROM, every Read, Program and Erase operations are performed under a stable and strong VCC supply connected to pin1. In the event that VCC in pin1 is removed, all on-going Read, Program and Erase operations will be interrupted and fail because there is no second source of VCC that can immediately replace VCC in pin1 to complete the operation. Although EEPROM is a non-volatile memory, the new data during the HV erase or HV program course would get corrupted.
Since this I2C package has three address pins of A0, A1 and A2, thus a total of eight I2C EEPROMs can be connected in I2C memory system when the density requirement needs to be expanded from one to eight. The rotated TSSOP package shown on the right also indicates an 8-pin configuration without any Vbat and Vcap pins with a primary LV VCC supply at pin2.
While traditional SRAM is a volatile memory technology so that its data cannot be retained permanently once the VCC power supply is being removed. But the VM SRAM memory has one great advantage over the NVM memories of NAND and EEPROM. The SRAM has unlimited P/E endurance cycles.
FIG. 2 shows a Vcap assigned to pin1 to replace A0 for a regular 8-pin I2C Serial NVSRAM product. The VCC in pin8 is the first regular VCC power supply, while the Vcap in pin1 acts as the second VCC back-up supply. In a normal NVSRAM operation, the pin1 Vcap is always being fully charged to a VCC voltage level by drawing charges from VCC in pin8 through one VCC switch circuit controlled by the on-chip state machine.
When the VCC power in pin8 is pulled down due to power loss below a predetermined value such as 80% of a full VCC value, then the internal VCC detector would immediately switch and connect the on-chip common VCC power supply lines to the second back-up off-chip Vcap at pin1, which is always kept in a full-charge state before the VCC power loss occurs at pin8. This VCC power switching has to be completed promptly to meet a specification of less than few ms before the internal SRAM VM data is corrupted and lost.
Despite an off-chip Vcap in pin1, it can quickly replace the falling VCC in pin 8 in today's NVSRAM design, one drawback is that NVSRAM still takes a long time and consumes high VCC power from Vcap to commence the on-chip VPP pump, oscillator and the associated logic control circuits to ensure that the operation of the “Store” operation is securely performed without losing any SRAM data upon the VCC power loss at pin8.
Both the logic control and VPP (or VNN) pump circuits draw huge VCC power from the Vcap at pin1 after VCC power loss at pin8. The charges of Vcap flows into internal VCC buses through the pin1 inductance 10 nH of pin1 bonding wire. Currently, the NVSRAM Store operation undergoes two VCC-power-intensive HV steps of erase first and program later. That means both VNN pump and VPP pump are involved along with their associated oscillators. Plus the on-chip state machine that controls these control sequences also draw a substantial VCC current. As a result, the size and value of the Vcap capacitance become very crucial at pin1.
Typically, the average Vcap value is around 100 uF for a NVSRAM memory density below 4 Mb to sustain few hours for normal operation. The unit price of a typical Vcap varies from $0.1 to $1 with a big footprint, depending on the purchased quantity and quality.
There are variants that include an on-chip battery to maintain the operation of SRAM device in the event of an unexpected power loss. Known as BBSRAM, this type of memory requires a large physical size because the battery, power management circuitry and the SRAM are combined into a single package. BBSRAMs are generally optimized to conserve battery power since the small battery has limited power, so low-power SRAMs must be used. Unfortunately, an attribute of low-power SRAMs is its slower access time, making them unsuitable for many medical applications like infusion pumps.
FIG. 3 shows a battery, Vbat, connection being assigned to pin7 for a regular 8-pin SPI Serial NVSRAM product. The VCC in pin8 is still the first regular VCC power supply, while Vbat in pin7 acts as the second VCC back-up supply.
This is called the 8-pin Serial-type BBSRAM, a Battery-Backed SRAM. Internally, there is no any kind of on-chip NVM. The whole BBSRAM is a SRAM silicon die packaged with an off-chip battery with a connection in pin7. This BBSRAM chip can be configured into either I2C or SPI serial type memory. Due to the adding of a battery, each BBSRAM memory would have the advantage of blending the performances of a regular VM SRAM with high-speed read and write plus the non-volatile feature of Flash.
Again, as seen from the above figures, Vbat has many disadvantages such as high cost, bulkiness, and concern over environmental handling. In addition, sooner or later, the power supply of Vbat would become used up. Before that, a constant monitoring of Vbat voltage level is required. As a result, the BBSRAM system is more complicate, thus the market share is smaller than its NVSRAM counterpart.
Another shortcoming of BBSRAM is the additional point of failure introduced by the battery due to its limited life span. Once the battery loses its ability to maintain a charge, the unit represents a significant risk because it is incapable of providing robust and secure backup of patient-critical data.
Because of the shortcomings encountered with these non-volatile memory types, an increasing number of manufacturers are using NVSRAMs. The NVSRAM is a memory technology that combines a high-speed SRAM with an equal amount of non-volatile Flash on the same chip.
During normal system operation, the NVSRAM behaves exactly as a standard fast SRAM with on-chip Flash part invisible to users and can be easily interfaced to the existing microprocessors. The NVSRAM constantly monitors its VCC supplied power, and if it detects an event that may cause a loss of VCC power, it automatically stores an exact copy of SRAM's contents to Flash in a single, and extremely fast, simultaneous transaction, usually referred as a “Store” operation. Even in the event that the normal off-chip VCC power is instantaneously removed from the NVSRAM, a claim of using small an external off-chip capacitor provides sufficient power to the device to ensure that all of the SRAM's contents are successfully copied to the Flash on chip accordingly.
When VCC power is restored to the system, the contents of the Flash are then automatically written back to the SRAM, returning the system back to the same state as before the disruption of VCC power. Typically, this process is referred as a “Recall” operation of NVSRAM.
Since the vast majority of repetitive write operations take place with the on-chip SRAM, there is no possibility of memory degradation or wear-out. Without an on-chip SRAM, the 100K P/E endurance cycles of a Flash cell can only withstand more than 25 power interruptions per day over the typical 10-year lifespan of a semiconductor device.
Within the NVSRAM memory chip design today, there is no immediate availability of two strong and stable on-chip HV VPP and LD VCC power supplies required by the “Store” operation upon the sudden loss or removal of an external VCC power supply during the regular SRAM's Read and Write operations.
Despite today's 12T NVSRAM system has one off-chip back-up VCC capacitor, Vcap, but to obtain an on-chip stable HV VPP without a strong powerful Vbat supply to complete a desired “Auto-Store” operation still faces many tough challenges. This is because a sequence of critical and risky steps has to be successfully performed to complete the Auto-Store operation of the NVSRAM memory.
Depending on the NVSRAM design, in one case, the “Auto-Store” operation involves two HV critical steps in sequence such as the first step of a −15V VNN FN-channel erase operation followed by the second step of a +15V VPP FN-channel Program operation. All these operations are guided by the on-chip State-machine design to perform on the large-density NVSRAM's flash cells. All these VPP & VNN pumps and the State-machine circuits consume VCC power that is supplied by either a weak Vcap or a strong Vbat off-chip.
As a result, the Vcap capacitance value becomes very critical. Similarly, constant monitoring Vbat voltage level is also very crucial. For example, according to Cypress' NVSRAM specification, Vcap value more than 100 uF is required. FIG. 4 shows below three packages with Vcap pin as a second back-up VCC at pin30, pin1 and pin36 from left to right for 44-pin TSOP, 48-pin SSOP and 54-pin TSOP packages of the SPI Parallel NVSRAM product. There are two regular first VCC supplies at pin11 and pin33 for 44-pinTSOP, another two regular first VCC supplies at pin25 and pin48 for 48-pinTSSOP and another two first VCC supplies at pin13 and pin 41 for 54-pin TSOP. A Vcap connection is assigned to pin30 in 44-pin TSOP package, to pin1 in 48-pin SSOP package and to pin36 in 64-pin TSOP package for a variety of the Parallel NVSRAM chips.
Similar to a Serial-type NBSRAM, the added Vcap is bulky and costly and the operation of “Auto-Store” takes lengthy delay because of the complicated logic controls for performing both erase and program operation that requires two HV voltages of VPP and VNN that require few ms to charge up to the desired +15V and −15V to whole NVSRAM flash cells' gate with a high capacitance loading.
In summary, today's NVSRAM devices combine the best attributes of SRAM's fast unlimited Read and write cycles and Flash NVM capability retaining data after VCC power loss as an alternative robust and safe data repetitive storage device. But the shortcoming is a need of an off-chip battery, Vbat, or an off-chip VCC back-up capacitor, Vcap, and the complicated timing control sequence that loads a heavy burden on system microprocessor's design. The result is its slower introduction to the market place.
In addition, either Vcap or Vbat approach stores only a LV VCC supply voltage at an external pin. When a regular VCC power loss is detected and NVSRAM switches to connect them, they still provide none of the instant VPP on-chip power supply. It will takes few ms to enable the on-chip oscillator and charge-pump circuits and a complicate State-machine design to provide the control over the Erase and Program operations during the power-down period.
Therefore a cautious constantly monitoring of the Vbat power system is required, that makes the NVSRAM system costly. Plus Vbat battery has another environmental handling issue. Thus, the acceptance in market place declines.
Note, in some flash occasions, the erase and program definition may be reversed. For example, an erase operation is defined to decrease flash cell's Vt by applying a negative HV VNN (−15V) on cell's gate with cell's channel held at ground with a program operation being defined to increase flash cell's Vt by applying a positive HV (+15V) to cell's gate. Conversely, an erase operation is defined to increase flash cell's Vt by applying a positive HV VPP (+15V) on cell's gate with cell's channel held at ground with a program operation being defined to decrease flash cell's Vt by applying a negative HV (−15V) to cell's gate.
In view of above drawbacks of off-chip Vcap and Vbat NVSRAM system designs, it is desired to develop improved techniques in NVSRAM auto-store function upon VCC power loss without complicated state-machine design for VCC power saving with high-yield success.